1. Technical Field
The embodiments described herein relate to a semiconductor memory apparatus, and more particularly, to a semiconductor memory apparatus that is capable of stably performing a data input operation.
2. Related Art
An exemplary semiconductor memory apparatus includes a plurality of data input buffers and a plurality of data strobe clock buffers. In an advanced semiconductor memory apparatus, for example, a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), data bits, which are serially input through data input buffers, are individually latched in a plurality of latch circuits under the control of a data strobe clock signal, aligned in a MUX circuit, and transmitted to a data input sense amplifier in parallel. Then, the data input sense amplifier receives the plurality of data bits transmitted in parallel and transmits them to a global line under the control of a data input strobe signal. The semiconductor memory apparatus includes a data input strobe signal generating circuit, and generates the data input strobe signal in response to an external clock signal and a write command signal.
Since apparatuses, which are located outside the semiconductor memory apparatus and transmit data bits to the semiconductor memory apparatus, do not operate with the same timing, all of the data bits are not input to the semiconductor memory apparatus with the same timing.
Accordingly, a time margin between the input data bits and the external clock signal of the semiconductor memory apparatus functions as an important factor to stably perform a data input operation. However, as the operation speed of the semiconductor memory apparatus increases, the time margin between the input data bits and the external clock signal has been reduced. As a result, it becomes increasingly difficult to stably perform a data input operation. FIG. 1 illustrates the stability problem when data bits are input at a high frequency.
FIG. 1 shows two cases with respect to timing relation between four data bits ‘d1’ to ‘d4’, which are input in serial to a data input circuit, and an external clock signal ‘CLK_EXT’. In the first case, data bits ‘d1’ to ‘d4’ are input with relatively advanced timing on the basis of the external clock signal ‘CLK_EXT’. Meanwhile, in the second case, as compared with the first case, the data bits ‘d1’ to ‘d4’ are input with relatively delayed timing on the basis of the external clock signal ‘CLK_EXT’.
As such, the input timing of the data bits is not constant. Thus, a data input strobe signal ‘dinstb’ needs to be enabled so as to ensure an accurate operation of the data input circuit. However, in a high frequency clock signal environment, the regions surrounded by the dotted lines in FIG. 1 become extremely narrow. As a result, generation timing of the data input strobe signal ‘dinstb’ is not constant or the data input strobe signal ‘dinstb’ is not generated.
That is, due to an increase in the operation speed of conventional semiconductor memory apparatus, the timing margin of the data input strobe signal has been reduced, which lowers stability of the data input circuit in a conventional semiconductor memory apparatus.